> I am having a problem What *IS* the problem ? And also, that code must have a lot that isn't needed to show the problem, doesn't it. Try to strip it down to the bare minimum of code that still shows your "problem". Chanses are that you'll find the problem while doing that... Jan-Erik. Harry H. Arends wrote: > I am having a problem moving some code from a 628A to a 685 device. Its > regarding a signal that is placed on RB7 that triggers a interrupt and then > runs a interrupt routine. Both the init code as the interrupt code is down > below. Could someone have a look and give a suggestion what is wrong. The > reason that i change to this device it the use of the PWM module that is not > in this form on the 16F628A. > > errorlevel -305, -302 ; suppress Bank warnings > list p=16F685,r=hex > INCLUDE "P16F685.INC" > __CONFIG 0x3CE2 > > ; --- Constant values > FXTAL equ D'8000000' > > RA_TRIS equ 0x10 ; RA4: input > RB_TRIS equ 0x80 ; RB7: input > RC_TRIS equ 0x00 ;*All outputs > > RA_INI equ 0x00 ; all zero > RB_INI equ 0x00 ; all zero > RC_INI equ 0x00 ;*all zero > > OPTION_INI equ 0x88 ; Option register: no pull-up, no prescaler, wdt 1:1 > INTC_INI equ 0x88 ; GIE, RBIE enable, PEIE disable > PIE1_INI equ 0x00 ; no interrupts > > #define OUT1A 0 ; Semaphore 1. Port A > #define OUT1B 1 ; > #define OUT2A 2 ; Semaphore 2 > #define OUT2B 3 ; > #define OUT3A 4 ; Semaphore 3. Port B > #define OUT3B 5 ; > #define OUT4A 6 ; Semaphore 4 > #define OUT4B 7 ; > ;#define SWITCH PORTB,5 ; switch > #define ACKOUT PORTB,6 ; acknowledge > #define DCCIN PORTB,7 ; DCC input pin > > ; --- Bank 0 > #define RAMINI0 0x020 ; 80 bytes > SHIFT0 equ RAMINI0+0x02 > SHIFT1 equ RAMINI0+0x03 ; interrupt shift register > SHIFT2 equ RAMINI0+0x04 > SHIFT3 equ RAMINI0+0x05 > SHIFT4 equ RAMINI0+0x06 > SHIFT5 equ RAMINI0+0x07 > DATA00 equ RAMINI0+0x08 > DATA0 equ RAMINI0+0x09 ; received packet > DATA1 equ RAMINI0+0x0A > DATA2 equ RAMINI0+0x0B > DATA3 equ RAMINI0+0x0C > > PAGEREG equ RAMINI0+0x0D ; Page register > > FLAGS equ RAMINI0+0x40 > > ; --- Flags > #define NEW_PACKET FLAGS,0 ; New packet received > #define NOCV FLAGS,1 ; No CV finded > #define RDONLY FLAGS,2 ; CV read only > #define DCC4BYTE FLAGS,3 ; DCC command 4 bytes > #define PROG_2X FLAGS,6 ; 2x prog > #define RESET_FLG FLAGS,7 ; reset packet > > ; --------------- Program Section -------------------------------------- > org 0x000 > > PowerUp: > clrf STATUS ; Bank 0 default > clrf INTCON ; Disable all interrupts > clrf PCLATH ; tables on page 0 > goto INIT > > ; ---------------------------------------------------------------------- > org 0x004 > > Interrupt: > movwf INT_W ; save context registers ;1 > swapf STATUS,w ;2 > movwf INT_STAT ;3 > clrf STATUS ; interrupt uses bank 0 ;4 > > btfsc DCCIN ;5 > goto Int_High_Half ;6,7 > Int_Low_Half: > movlw d'256' - d'154' ; 77us: between 64us (one) and 90us (zero);7 > movwf TMR0 ;8 > bcf INTCON,T0IF ; clear overflow flag for counting ;9 > > bcf INTCON,RABIF ;*10 > goto EndInt ;13,14 > > ; 1111111111 CCCCCCCC 0 AAAAAAAA 0 DDDDDDDD 0 EEEEEEEE 1 > ; 'x1111111''111 0 CCCC''CCCC 0 AAA' 'AAAAA 0 DD' DDDDDD 0 E' 'EEEEEEE 1' > ; SHIFT0 SHIFT1 SHIFT2 SHIFT3 SHIFT4 SHIFT5 > > ; 1111111111 0 AAAAAAAA 0 DDDDDDDD 0 EEEEEEEE 1 > ; 'xxxxxxxx''xx111111''1111 0 AAA' 'AAAAA 0 DD' DDDDDD 0 E' 'EEEEEEE 1' > ; SHIFT0 SHIFT1 SHIFT2 SHIFT3 SHIFT4 SHIFT5 > > > Int_High_Half: > bsf STATUS,C ;8 > btfsc INTCON,T0IF ; if timer 0 overflows then is a DCC zero;9 > bcf STATUS,C ;10 > rlf SHIFT5,f ; receiver shift register ;11 > rlf SHIFT4,f ;12 > rlf SHIFT3,f ;13 > rlf SHIFT2,f ;14 > rlf SHIFT1,f ;15 > rlf SHIFT0,f ;16 > > movlw 0xC0 ; ignore older bits ;17 > iorwf SHIFT1,w ; ;18 > xorlw 0xFF ;'xx111111' ? first 6 preamble bits ;19 > btfss STATUS,Z ;20 > goto Int_High_Check4 ;21,22 > > Int_High_Check3: > movlw 0xF8 ; check 4 preamble and start bit ;23 > andwf SHIFT2,w ; '1111 0 xxx' ;24 > xorlw 0xF0 ;25 > btfss STATUS,Z ; ;26 > goto EndHighHalf ;27,28 > > btfss SHIFT5,0 ; check end bit ;29 > goto EndHighHalf ; is zero, may be 4 byte packet ;30,31 > > bsf NEW_PACKET ; fill received packet ;31 > movf SHIFT5,w ;32 > movwf DATA3 ;33 > movf SHIFT4,w ;34 > movwf DATA2 ;35 > movf SHIFT3,w ;36 > movwf DATA1 ;37 > movf SHIFT2,w ;38 > movwf DATA0 ;39 > clrf SHIFT1 ; prevent 4 byte command decoding ;40 > > EndHighHalf: > bcf INTCON,RABIF ;46 ;31 > EndInt: > swapf INT_STAT,w ; restore context registers ;49 ;34 > movwf STATUS ;50 ;35 > swapf INT_W,f ;51 ;36 > swapf INT_W,w ;52 ;37 > retfie ;53,54 ;38,39 > > > Int_High_Check4: > bsf SHIFT0,7 ; command 4 bytes, check 7 preamble bits;23 > incfsz SHIFT0,w ;'x1111111' ;24 > goto EndHighHalf ;25,26 > > movlw 0xF0 ; check 4 preamble and start bit ;26 > andwf SHIFT1,w ; '1111 0 xxx' ;27 > xorlw 0xE0 ;28 > btfss STATUS,Z ; ;29 > goto EndHighHalf ;30,31 > > bsf NEW_PACKET ; fill received packet ;32 > bsf DCC4BYTE ; command 4 bytes ;33 > movf SHIFT5,w ;34 > movwf DATA3 ;35 > movf SHIFT4,w ;36 > movwf DATA2 ;37 > movf SHIFT3,w ;38 > movwf DATA1 ;39 > movf SHIFT2,w ;40 > movwf DATA0 ;41 > movf SHIFT1,w ;42 > movwf DATA00 ;43 > goto EndHighHalf ;44,45 > > > ; ---------------------------------------------------------------------- > INIT: > clrf PORTA > clrf PORTB > clrf PORTC ;* > clrf PIR1 > movlw 0x31 ; Timer 1 on, 1:8 > movwf T1CON > > BANKSEL TRISB ;*Bank 1 > movlw RA_TRIS ; Set port A I/O configuration > movwf TRISA > movlw RB_TRIS ;*Set port B I/O configuration > movwf TRISB > movlw RC_TRIS ;*Set port C I/O configuration > movwf TRISC > > clrf WPUA ;*Do not use WeakPullUp on port A > clrf IOCA ;*Disable all Interrupt On Change register A > movlw PIE1_INI > movwf PIE1 > movwf PIE2 ;*In 16F628A not implemented > movlw OPTION_INI ; Option register: no pull-up, no prescaler, wdt 1:1 > movwf OPTION_REG > > BANKSEL ANSEL ;*Bank 2 > clrf ANSEL ;*Set to all Digital > clrf ANSELH ;* > clrf WPUB ;*Disable WeakPullUp on port B > movlw b'10000000' ;*Set RB7 to Interrupt On Change, rest off > clrf VRCON ; voltage reference off > clrf CM1CON0 ;*Switch off Comparators > BANKSEL 0x00 ;*Bank 0 > > movlw 0x20 ; clear RAM > movwf FSR > ClearRAM: > clrf INDF > incf FSR,f > movlw 0x50 > xorwf FSR,w > btfss STATUS,Z > goto ClearRAM > > movlw INTC_INI > movwf INTCON ; enable RB4..7 change interrupt > > clrf PAGEREG ; page register default > > call LoadCV ; load CV values > > btfsc SAVE_OUTPUTS ; load saved outputs > call LoadOutputs > > movlw d'2' ; init slope counter > movwf ACC_COUNT > > ; ---------------------------------------------------------------------- > > MainLoop: > goto MainLoop > > I know the code is not looking prity but its copied from MPLAB IDE v8.10 > > Regards > > Harry > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist