Hey,Paul.We are a PCB Manufacturer and I will inquiry our engineer if they know. we make 1-10 layer PCB.Material:FR-4,aluminium,FPC.thickness:0.4-4.2mm,min.Line/Space:0.1mm,min.hole:0.1mm,inculding burried/blind hole.Details pls send me email by hanward@szckt.cn or contact me at: Contacting:Hanward Jiang Marketing Dept.Manager Cirket Electronics Company 22A,Block B,Nanhai Bldg,Nanshan Rd, Shenzhen,P.R.China Tel:+86-755-8621 5150 Fax:+86-755-8621 5160 MSN:hanwardjiang@hotmail.com Skype: hanward Website:www.szckt.cn PAUL James-3 wrote: > > All, > > Another thing to keep in mind when laying out the traces is make loop > size as small as possible. > For instance, if you have a differential input, make the two conductors > go side by side as much as possible. > Don't let them stray apart. The same thing goes for outputs, but less > so than inputs. > > The theroy behing this is that the larger the loop, the greater the area > for EM signal to intercept the conductors, > thereby inducing currents into the circuit that shouldn't be there. Or > in other words, the larger the loop area, > the better the antenna you have created for reception of Lord knows what > to get into your circuitry. > > Just something to keep in mind. > > > > > > Regards, > > > Jim > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > > :clap::clap: -- View this message in context: http://www.nabble.com/PCB-Layout-tp18969194p18973881.html Sent from the PIC - [EE] mailing list archive at Nabble.com. -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist