Thanks Dennis.

Tried multiple PICs, I don't believe I had the problem when the TX unit 
was in a solderless breadboard, but that could mean anything. The 
circuit is now 'established' in a hand-made PCB, so I am somewhat 
reluctant to cut traces and rewire it. I also 'potted' the board with 
epoxy to stop the copper from oxidising. Access is a little problmatic.

Still, I have changed the 1M pull downs to 100K, and found a potential 
bridge under a 1206 resistor.

The only change in the code since I posted it was to add 'bcf 
STATUS,RP0' to the ISR after saving away the STATUS register. (updated, 
I also bcf INTCON,T0IE after the second fn_broadcast).

Further analysis of mine indicates that the PIC is not likely to be in 
the ISR with RP0 set (high memory bank). The interrupts will never be 
enabled at any point when the main loop is in the high bank. Hmm, 
actually, they may be... which is a bug too. Fixed now, although the 
timing of the TMR0 is such that I don't believe that the ISR is entered 
at when in Bank 1. I offer as evidence, that, if that were to happen, 
the check for the PIR1,ADIF flag would actually hit the PIE1 register, 
and swithc off the A/D Interrupt enable, causing the A/D sleep operation 
to never exit till the WDT reset a full 2.3 seconds later...

This would be very obvious to me since the receiver would complain lots 
and lots about a missed transmission. Further, the A/D setting would 
never be reset to on, so, there would always be 5 seconds between 
transmisions instead of 2.5. No, that's wrong. If the ADIE were set to 
0, the A/D sleep instruction would reset the PIC and the ADIE will be 
reset in the initialization routine to 1. Which will mean just one 
glitch which I may miss...

All very confusing for a simple project.

Well, it is bed time for me. Let's see what has happened in the morning.

Thanks again


P.S. hope you don't waste time on this. I am thinking that the most 
logical answer to my riddle was the solder paste under R1. But, it is 
very weird how it manifest with a 'delayed' activation. There were times 
in the past few days where I have felt that physically manipulating the 
board has 'fixed' the problem, but I always deemed that to be a result 
of my fingers changing the capacitive load somewhere.... but, it may 
have been me 'jiggling' the bridge under R1.

Anyway, the code is relatively presentable, and I have been racking my 
brain for a few days, so I would greatly appreciate another pair of eyes 
to see anything else I may have missed.

Regradless, until it manifests again I am calling it 'case closed'.

Rolf


Dennis Crawley wrote:
> On Sunday, June 29, 2008 5:30 PM [GMT-3=CET],
> Rolf  wrote:
>
>   
>> Hi all.
>>
>> Nope, problem still there. Somewhere between 2.5 and 3 hours to manifest
>> this time.
>>
>> Anyone? ;-)
>>
>> Rolf
>>     
>
> Rolf,
> I know is somewhat anoying, but Do you have the same problem when you test
> it over your working table?
> I don't think you have noise.
>
> Since this is the unique pin that makes you crazy, why you don't use another
> pin? or switch the function pin to another?, or try with another pic?,...
> just to be sure is not the damn pic.
>
> I'll dig into the code now.
> bye
> Dennis
>
>
>
>
>   

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