On Fri, Jun 27, 2008 at 8:53 PM, Olin Lathrop wrote: > Switching losses start to dominate as the switching > transition time because a significant fraction of the switch on time per > pulse. Higher voltages require shorter pulses with everything else held > constant for some configurations. I think this probably your main > objection. Firstly thanks for putting efforts so that others can understand. Some people here clearly do not under even the basics of buck converter. Modern MOSFETs are pretty good and have low Rds-on and tends to have higher switching frequency, and switching losses are often the dominate. So yes this was what I mind. But it is more than this. Even with more traditional lower switching frequency buck converter (MOSFET + free-wheeling diode), where conduction loss is the dominating factor, lower duty ratio is still not desired as the free-wheeling diode will conduct most of the time and thus have higher loss due to the diode voltage drop. That is why synchronous buck converter becomes more and more popular in many applications. > I have no doubt that you have experience with power supplies that are less > efficient at higher input voltages. Design tradeoffs can certainly be made > where that would be the case. But you have to stop and realize this general > tradeoff is not a universal rule, but rather a characteristic of specific > (perhaps even common) designs. I would say common design is what I had in mind. I would not say it is a universal rule but it is kind of a common sense within the filed of power electronics that you do not want the duty cycle to be as low as 0.05. Regards, Xiaofan -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist