The relationship between Id and Vgs for any kind of P channel FET (put Id
on Y axis, Vgs on X) is the right half of a parabola facing up with the
vertex on the X axis. As you move to the right, increasing Vgs, the
current goes up.

For a J-FET, the vertex is to the left of the Y-axis. The X value where Id
goes to zero (the vertex) is the cutoff voltage. The current when Vgs is
zero (at the Y axis) is Idss. With an N-channel JFET, you cannot drive the
gate positive or the junction will start to conduct.

Once you move to MOSFETs, there are depletion mode and enhancement mode
FETs. With these, the gate can be driven positive with respect to the
source. These have the same Id vs Vgs curve (a half parabola), but the
curve can be slid to the right. A depletion mode FET may have the curve
about where a JFET is, that is, Vgs=0 will have drain current. Driving the
gate negative decreases the drain current. Driving it positive increases
the drain current.

An enhancement mode MOSFET (most common), has the half parabola slid to
the right so Id does not start to increase until Vgs is positive.

The main electrical differences are where the vertex of the half parabola
is. And, don't drive the JFET gate positive.

For P channel, reverse all voltages and currents!

Harold



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