At 07:04 AM 6/18/2008, you wrote:
>Olin Lathrop wrote:
> >
> > David Meiklejohn wrote:
> > > I'm just wondering how much "safety factor"
> > > is in the specs, in practice.
> >
> > No amount of your own testing can give you a reliable answer other than
> > "none".
>
>Very true.  Like I said, it's not something I'd do myself - I'm a firm
>believer in operating within published specs.  But, there's also such a
>thing as idle curiosity, the search for knowledge with no practical value,
>and all that!  :-)

Given the assumption that (based on solid-state physics and CMOS design)
there's a predictable change of maximum fosc with
temperature, one could probably quite safely get a small increase in fosc
above rated maximum by restricting the Tj range. Since Microchip do not
test every chip at temperature extremes, they would have to test the chips
to a tighter tolerance at room temperature to guarantee most chips will meet
specs at the extremes. I'd feel quite comfortable doing this in a production
situation, for example to get 20.48MHz =3D 5 * 4096MHz operation on a 20MHz
rated part by using a part rated and tested for (say) 125C=B0C at no more
than 60=B0C Tj (and thus perhaps 50=B0C Ta). This might be important to gen=
erate
a low-jitter high speed clock at a specific "odd" frequency, for example.

Of course even so there's a small amount of risk in this, and the safe
improvement is not a very high percentage-- and there are usually better
choices that don't require this sort of thing, so I don't recommend it.

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the rewar=
d"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com




-- =

http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist