Guys, before you go till the first blood, take a look at that datasheet again. It could be confusing as in Table 4-1 and 4-2 does not even mention anything about paging with the FSR. In fact, with the 12F510 they even mention a wrong power-on reset value (100x xxxx, however only bit 5 is used as banking). The only indication that something is weird with FSR is that the upper 3 bits are not full set after the POR. Same mistake with the 12C5xx and 12F508/12F509/16F505 datasheets. Tamas On Mon, Jun 16, 2008 at 12:19 AM, David Meiklejohn wrote: > Nicola Perotto wrote: > > > You are right, I simplified because my english is bad... > > What I wnated to say is that FSR is a simple pointer with no particolar > > use of any bit (of course if the memory is small some bit are unused). > > > > > >> Nicola Perotto wrote: > >> > >>> Hi David, > >>> you are completely wrong! > >>> I just read the datasheet of 10F220, 12F629 amd 12F510 and the FSR > >>> register is always an whole 8 bit data pointer. > > Nicola - before you say I'm completely wrong, go read that 12F510 data > sheet again. > > I agree that on the 10Fs, the upper 3 bits of FSR are not used for paging > - because the 10Fs only have a single page (as Olin said). And since the > 12F629 is a midrange device (unlike 10F* and 12F5*), FSR isn't used for > paging. > > But - please go back and look at page 25 of the 12F510 data sheet > (DS41268D). Bit 5 of FSR is used for bank select - for direct addressing. > So on the 12F510 (and 12F509, 16F505, 16F506, 16F57, 16F59 etc.) FSR is > in fact used in direct addressing. Not just indirect. > > > David Meiklejohn > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- Rudonix DoubleSaver http://www.rudonix.com -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist