Electron wrote:
> Hi!
>
> This dsPIC code sequence:
>                         MOV.B           #0xE0,W0
>                         MOV.B           WREG,SR
>
> does NOT disable the IRQ's.
>
> I'm quite desperate.. why's that?
>
> I tried to write 0xFFFF to the register, and what I read back is 0x010F,
> i.e. the IPL bits seem not writable!
>
> Even setting bit IPL3 in CORCON doesn't prevent interrupts from occuring.
>
> Sure, I can disable the sources, but since I've worked up the prioprities
> for them carefully, the best way would be the one that seems by design for
> the dsPIC, i.e. to set a minimum interruptable level in SR! But it doesn't
> work!
>
> Thanks,
> Mario
>
>   
First, may we have a little background first? Which chip? Have you set 
your configuration in code, or have you used the configuration tool in 
MPLAB?
Second, you may already be aware of this but, some bits of the SR 
register cannot be written to. Bit 0-4 are read/write, bits 5-7 (the IPL 
bits) are read/write, bit 8 is read/write, bits 10,12,and 13 are 
read/clear, and the others are read only (in the 30F2010 at least). This 
is why you get the results you have seen when trying to write 0xFFFF to 
the SR register.
In the CORCON register, IPL3 (which is a read/clear bit) is concatenated 
with the IPL bits of the SR register (bits 5-7) to set the processor 
interrupt priority, not to enable or disable interrupts (however the 
docs do say that setting bits 5-7 sets processor interrupt priority at 7 
thus disabling user interrupts). The dsPIC has nonmaskasble (cannot 
disable) interrupts for core cpu functions.
Which interrupts are you trying to disable?

-- 
Regards,
Stephen D. Barnes

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist