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After re-reading for the nth time all datasheets, I found it by myself:

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Note: The IPL<2:0> bits become read only bits when interrupt nesting is d=
isabled. See Section 6.2.4.2 =94Interrupt Nesting=94 for more information.

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I had disabled Interrupt Nesting due to a bug of this chip revision.. :/

Now I have to choose from two evils.

Greets,
Mario


At 15.38 2008.06.02, you wrote:
>
>Hi!
>
>This dsPIC code sequence:
>                        MOV.B           #0xE0,W0
>                        MOV.B           WREG,SR
>
>does NOT disable the IRQ's.
>
>I'm quite desperate.. why's that?
>
>I tried to write 0xFFFF to the register, and what I read back is 0x010F,
>i.e. the IPL bits seem not writable!
>
>Even setting bit IPL3 in CORCON doesn't prevent interrupts from occuring.
>
>Sure, I can disable the sources, but since I've worked up the priopritie=
s
>for them carefully, the best way would be the one that seems by design f=
or
>the dsPIC, i.e. to set a minimum interruptable level in SR! But it doesn=
't
>work!
>
>Thanks,
>Mario
>
>--=20
>http://www.piclist.com PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

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