On Wed, May 21, 2008 at 6:48 PM, Rolf wrote: > The simplest thing is to set the most significant bit of the TMR1H byte > very soon after the TMR1 interrupt.... (to be absolutely safe, it must > be within 256 ticks of TMR1 or 7.8ms). > > bsf TMR1H,7 > > What this does is cause the interrupt to happen in exactly 1 time per > second .... ;-) Good idea (update only the high byte, let the low one run) but it won't work. >From the datasheet: The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. Regards, Mark markrages@gamil -- Mark Rages, Engineer Midwest Telecine LLC markrages@midwesttelecine.com -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist