Hi Matt,

First of all, I this does not seem right in the set_tx_bit routine:

        decfsz  bit_count, F
        incf    state, F        ; All the bits have been set, advance to the
next state.

Secondly, I thing you should wait at the beginning to settle the line in
stop mode at least 1T but possibly better to wait 2T before you put the line
low with the start bit. After then you can keep going with the 8N1 settings
you are using - actually I was not sure if the time you are waiting to send
the stop bit is ok - it has to be 1T at least...

Tamas



On Wed, May 14, 2008 at 4:58 AM, Matthew Miller <namiller2@naxs.net> wrote:

> On Tue, May 13, 2008 at 11:32:55PM -0400, DavidCOU@aol.com wrote:
> > But, on the next Byte received (or in the Test IOC); I do not see where
> the
> > STATE is cleared in the INT version.
> >
> > I do see your foreground remnant does clear the STATE though.
>
> The state variable is cleared in the "receive" routine. But this isn't too
> important: I'm testing the transmit code and it is this that isn't
> working. The receive stuff can wait. :)
>
> I have two transmit routines, one which works and the other doesn't. I
> don't
> know why the interrupt version doesn't work and I hope someone can show me
> the error.
>
> Thanks.  Matt
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