Thank you all for the thoughtful feedback.  Sorry, it took so long to 
reply.  I took me a while to find the archive where I could read the 
replies.  Last time our IT guy whined when about mail traffic when I 
signed up for PICList so this time a signed up for daily digest format.

Basically I am trying to replace a byte addressable serial EEPROM with 
the large flash memory space found in the newer PIC16F parts.  I had not 
thought about word-aligning as suggested by Forrest.  This would 
certainly make it easier for the math challenged (this includes myself); 
8-bit align in 14-bit words till end of memory space, then 4-bit align 
in the upper part of the 6-bits till end of memory space,  then 2-bit 
align in the remaining 2-bits of the upper 6-bits.  Performance would 
likely be faster than a math routine to calculate byte and bit offset.  
At least for the byte and nibble aligned address space; getting four 
2-bit chunks from four words might be as slow as a math routing.

I am still digesting the math routine ideas....

Thanks for the great input!

-Ed

Ed Sutton wrote:
> Are there other ways to implement a divide by a 14 constant other than 
> cycle-chewing subtraction loops?
>
> I want to use the PIC16F flash consisting of 14-bit words to store 
> 8-bit data.  I can implement the multiply-by-8 as a shift.  The crux 
> of the problem is basically the divide by a constant of 14.
>
> Pseudo Code ( actual code will likely be assembly )
>
> wordOffset = 8*byteOffset / 14;          // The integer result 
> wordBitOffset = 8*byteOffset % 14;   // The remainder result
>
>
> Patterns:
>
> The 14-bit words and 8-bit data have a common multiple of 56.
> The wordBitOffset pattern { 0,8,2,10,4,12,6 } repeats every 7-bytes.
> I can't see a solution but it is an interesting puzzle.
>
> Thanks in advance for any tips or suggestions,
>
> -Ed
>

-- 
Best regards,

-Ed Sutton

Engineering and Technical Support
esutton@engius.com

Engius, LLC 	
712 Eastgate St.
Stillwater, OK 74074
(866) 636-4487 Office
(866) 277-8369 Fax


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