Hello again,
I tried a bit different way to debug the situation. I enabled usart
recieve interrupts and set up a function to record that interrupt with
a simple RB0 level swap. However, I don't see RB0 changing levels at
all, which possibly means the reciever is not interrupting at all?
Here is the source for the reciever:
################################################
static void interrupt
isr(void)                       // Here be interrupt function - the name is
        // unimportant.
{
        RB1 = 1;
        RB0 = 0;
}
void main(void) {
        OSCCON = 112;   //4Mhz
        GIE = 1;
        PEIE = 1;
        RCIE = 1;

################################################
All the rest is as before (changed BRGH to 1 and SPBRG to 25 to reduce
'error percentage').


On Tue, Apr 8, 2008 at 12:17 AM, Jinx <joecolquitt@clear.net.nz> wrote:
> > Despite the Microchip advertising to the contrary, I have never
>  > been able to get the Int RC  Osc to handle  RS232 with any
>  > degree of reliability. The reason is that the RC timing "wobbles"
>
>  I certainly don't trust the F88 8MHz IntRC, but had no problems
>  - so far - with 9600 comms between an 18F1320 (8MHz IntRC)
>  and a 48MHz (crystal) 18F4550
>
>  Originally I was using the 18F1320 USART then changed to timer-
>  based s/w as I wanted to use IOC. Either way, no failures yet. But
>  admitedly all testing has been at comfortable ambient. I think adding
>  a routine to the 18F1320 to measure 4550 bit-length will be needed
>  before the unit literally goes out in the field
>
>  --
>
>
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