I'm in a need of having a PIC16F628 do asyncronous transmission with transmit
echo on CSMA/CD bus (hobby stuff, Model rail, LocoNet(R) bus). I need to listen
to the bus and start transmitting -- so I was told -- within 2us window from
checking the last time that the bus is idle. The bus rate is 16.66 kbaud (60us
bit length).

Looking at PIC16F628 datasheet the matching baudrate might be with:

	 Fosc.: 4MHZ
	 SPBRG: 240
	 BRGH.: 0

The start of USART transmission in asyncronous mode is syncronized to
BRG and not just to writing of TXREX. So, the beginning of start bit
transmission is not excact at all -- at least not even near the 2us desired
window if looking at writing of TXREG.

Writing to SPBRG will reset the BRG. Does it mean it would transmit
instantly after writing to SPBRG in case there is something to write (SYNC
cleared, SPEN set TXEN set, TXREX written with data)? Could
one write 240 to SPBRG, write to TXREX and rewrite 240 to SPBRG to get the
transmission started immediately in case the LocoNet is still quiet? In case
LocNet would not be quiet one should clear TXEN and thus clear the transmitter
and start from the
beginning?

Possible sequence:

	 Write SPBRG, BRGH (start of Loconet bit 60us window)

	 Clear SYNC, Set SPEN
	 set TXEN
	 Write TXREX

	 While still within LocNet bit window:

	 check LocoNet is high?
	 Yes-> Write SPBRG (start xmit immediately)
	 No -> Clear TXEN and thus clear whole transmitter


Would this fail? One could get close to 2us -- with higher Fosc and SPBRG to
match even closer -- yes in case the transimmion starts at load of SPBRG and in
case all other pre-requisities are set?

In case writing 240 to SPBRG will cause exactly one LocoNet bit delay
of 60 us before xmitting the first start bit, writing 0 to SPBRG would cause
overflow within about 16 instructions and then one should check for LocoNet
being free until the 16 instr. cycles have gone, and in case all is still clear
let the transmitter start and have the next -- real SPBRG value fed before BRG
is looping back again. That might requre faster Fosc so that there would be
more time to get the correct seed to BRG through SPBRG with less length error
to  LocoNet START bit.

Possible sequence:

	 Write SPBRG, BRGH (start of Loconet bit window)

	 Clear SYNC, Set SPEN
	 set TXEN
	 Write TXREX

	 While still within BRG window:

	 check LocoNet is high?
	 No -> Clear TXEN and start all over
	 Yes-> Write 0 to SPBRG
	 count about 10--12 nop
	 check LocoNet is high?
	 No -> Clear TXEN and start all over
	 Yes-> Start of xmit after BRG: 0->overflow (16 instr)
	 Write SPBRG: 240

thus START bit would be about 3--4 intr.cycles longer than the rest
of the bits. 

Would this work?

My aim was to avoid using syncronous mode so that I could use receiver as
transmit echo to check collisions on byte width basis.

Yet another solution would be to make a hardware collision detect and use USART
in syncronous mode to start transmission exactly spot on ...

pekka



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