In SX Microcontrollers, SX/B Compiler and SX-Key Tool, robotworkshop wrote:

[quote="Kramer"]
It confirms what I suspected. The Timer1 interrupts are associated with Port B  [I guess there is a Timer2 that is tied to Port C that does the same] and can be fed into the Interrupt pathway that triggers the ISRs interrupt stack. So that is the source of your Serial I/O failure - two timers providing different ISR interrrupts.

I am not sure how SX/B presents this or if there is currently adequate isolation features in the software. It is really easier to study in assembly language and it appears that you have gotten the hang of it. Something needs to be considered and written about avoiding ISR conflicts when using these two timers.

I presume that Jon's ISR and the approach in his book is SX28 oriented: almost nothing has been explored and published about the SX48/52 timers.
 
You are doing pioneering with this topic.  I find it both interesting and wierd that the an ISR can be created with 3 interrupts or that the RTCC might be eliminated and one of the other Timers can generate a more complex IRS timer.  As I said about, this is exotic - but may not be useful.[/quote]

At the moment I think the only EXTRA interrupts are coming from TIMER1 as that is the one I am using.  As long as you don't touch them they are dormant and don't seem to generate any Interrupts at all.  Also, in regular PWM they don't generate an Interrupt either.  It only showed up when I switched to the TIMER mode which can generate Interrupts.  I've tried changing the small section of inline assembly code to set T1CNTA register to $DA instead which should prevent any Interrupts from coming from TIMER1 but it didn't seem to fix it.

I expected that other Interrupts would all go to the same ISR.  That may be desired in some cases and it would be up to the ISR code to determine what generated the Interrupt.  I think that it would also be possible to add a check to the beginning of the ISR to check to see if the Interrupt was due to the TIMER and if so just exit the ISR without hitting the Serial code.  At the moment the Serial code only expects to get executed at the specific any Interval defined at the beginning of the Interrupt code.  If other sources generate an Interrupt it just assumes that it is time to look for another bit coming down the Serial line.....

If I needed both Interrupts to be handled by the ISR then I suppose it could be rewritten to handle that.  I'd make the code at the very beginning of the ISR check to see what generated the Interrupt then branch accordingly to the appropriate section of code within the ISR to deal with it.

The part that is really bugging me about this problem is that the timers don't normally start generating Interrupts unless you use them in certain modes.  I just want to find a way to properly shut off a TIMER running in PWM mode so that it ends up in the same state it was before I started it.  There has got to be some way to do it but I haven't found the best method yet.

I don't think any of this is a problem with the SX48 chip.  We just need to get all the behavior documented so that there isn't any surprises.  At the very least the next update of the SX/B help file should probably have a note regarding the TIMER mode that by default it WILL generate Interrupts ad that when they are used you'll have to add code to your ISR to handle them.  

Another thing that would be cool for a future upgrade of SX/B would be an extra command like TIMER1 OFF to reset the state of the timer to put it back in it's initial state.  Another possible addition would be some command to easily set the timer configuration registers like TIMER1 CONFIG XXXX where XXXX could be the value to assign to the config registers for the timer specified.  Just throwing out a couple ideas for later.

So, I am still looking for a better way to turn off the PWM mode and will be watching the forum to see if anyone else may have something to add.

Robert

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