On Tue, 2008-01-22 at 06:33 -0500, Richard Seriani, Sr. wrote:
> According to the 25LC1024 datasheet, the internal write cycle time (byte or 
> page) is 6ms (max). I am doing page writes, so I load 256 bytes of converted 
> data into the EEPROM input buffer, bring !CS high to initiate the internal 
> write, then poll the status register WIP bit to check that the write is 
> complete.
> 
> Hmm, this means I am losing somewhere around 6ms of input for each 256 bytes 
> I am recording. Quick math shows that if I record about 31.25ms of audio for 
> each 256 bytes, I have about a 20% hole in the data. Does that sound right?
> 
> Okay, sounds like I need to look at some sort of double-buffering of the a-d 
> data? I think I may be able to load the 25LC1024 input buffer while the 
> array write is taking place, but I need to check that. If so, that may be 
> one solution that could be implemented simply by shifting a few instructions 
> in my code. I would load the buffer, then check the WIP bit to be sure the 
> write to the array is complete before I initiate the next write. The write 
> sould be complete since the conversion of 256 bytes will take about 5 times 
> as long as the EEPROM write cycle, so I may be able to get away without 
> checking it, though I am not sure I would want to.

The structure I've used for this sort of thing is a FIFO. Your ADC read
subroutine simple writes data to the FIFO, it doesn't care about
anything EEPROM. A second EEPROM routine keeps a look at the FIFO,
whenever it has more data then one page write it transfers the data to
the EEPROM and does the write.

That way the only thing you have to do to adjust for different sample
rates or EEPROM write times, or page size, is adjust the size of the
FIFO. Even make code reuse that much easier.

TTYL
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