Hi Russell, That's really interesting - I was not aware that avalanche operation was limited by second-breakdown type effects. MOSFETs have a negative temperature coefficient (increased temp gives less current) in the fully-on state (ohmic) and a positive temperature coefficient in the linear operating range (partially on - channel not inverted the whole way across between drain and source). This means that it is OK to parallel MOSFETs if they are to be operated in switch applications but not necessarily OK if they are going to spend significant time in the linear region. I have been bitten by this numerous times. Once, I made a constant-current battery discharger and used multiple FETs in parallel for the very reason that I thought they could always be paralleled. One got much hotter than the rest. A more interesting case of this I ran into more recently: I was using a pair of super low RdsON FETs in parallel in a 20kHz PWM application at around 80 Amps. I found that one of them would get much hotter than the other, even though the majority of the time they were purely ON or OFF. Amazingly, what I discovered (or at least hypothesized based on the data) is that the turn-on/off transient power dissipation was comparable to the I2R losses and since the transient power dissipation happens in linear mode, this means that during turn-on/turn-off, the hotter FET would take more of the current (effectively turn on faster, preventing the other from ever seeing a very large voltage and current at the same time). So, when paralleling FETs, sometimes low RdsON is a bad thing! I ended up solving the problem by turning the FETs on even faster, to keep the switching losses below the I2R losses, but that may not always be possible, in which case one may have to resort to higher RdsON or slower PWM. Sean On Dec 29, 2007 9:49 AM, Apptech wrote: > MOSFETs are usually deemed to be immune to the second > breakdown effects that cause problems in bipolar devices > (although this is not universally the case). While there is > some black magic involved, second breakdown is largely held > to be a localised thermal effect where current concentration > cause increased temperatures which cause current > concentration which cause ... oops. > > However, when operated in avalanche mode MOSFETs that are > not designed to rigorously distribute the current evenly > over their multiple subdevices tend to concentrate current > at selected sites with results that are not after the event > especially well distinguishable from having been > second-breakdowned. As SOA is not liable to be well defined > or defined at all in avalanche mode in a non avalanche > specified part YMMV and probably will if operating an > unrated part this way. > > > > Russell > > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist