On Wed, 2007-12-19 at 01:57 -0500, Sean Breheny wrote:
> Ok, but any idea on how to turn off those warnings selectively? Right
> now, I get thousands of warnings, a tiny fraction of which ARE
> relevant. Since I do care about glitches on output pins (or on clock
> or async reset nets), I don't want to turn off all glitch warnings.

Unfortunately I'm not familiar with the tool you are using.

As for glitches on outputs, there are two techniques to use:

1. Ignore them: if you're receiving logic is synchronous then you have
nothing to worry about, since each output will be sampled by a flop
before being used. Obviously if you're generating clocks or async resets
(as you mention) you can't go with this option for those nets...

2. Flop outputs: as long as the net comes from a flop output you don't
have to worry about glitches, there won't be any. For things like clocks
the best idea is to use the flop in the IOB of the FPGA, either generate
a 2X clock in the FPGA and then flop it in the IOB to generate the good
1X clock, or if your device has them use the DDR flops in the IOB to
generate your clock. This method results in a clock that will always
come out before any other net, very important. For async resets this is
usually also OK.

#2 also is good since it really frees up your tool with regards to
timing; it no longer has to deal with the long delays that might occur
with a net coming from the fabric and going to an IOB. I've seen
significant P&R speed increases from using this technique, never mind
the fact that when you start hitting high speeds (i.e. 150MHz+) you no
longer have to deal with incomplete P&Rs. I regularly do this for things
that are unidirectional and can be pipelined, like video.

With all that said, it sounds like you are generating clocks with the
fabric? Generally it's a much better idea to use the resources in your
part to generate/gate clocks, things like DCMs/PLLs can give you faster
clocks, things like PMCDs give you slower clocks. 

Clocks generated from the fabric can have very large skew with regards
to your input clocks, and this can result in bad behaviour (which the
tool won't warn you about unless you are properly constraining your
clocks). Using dedicated clock resources results in multiple clocks with
minimal skew.

TTYL

TTYL
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