In SX Microcontrollers, SX/B Compiler and SX-Key Tool, phipi wrote:

Bean,

Yup, something for which we can all be thankful! :-)

BTW, here's my ISR code for mixed interrupts on the SX28 family chips. As I said, it's less elegant than NetHog's solution, but it works:

[code]
ISR     MOV     W,#2            ;If RTCC low enough, then must be timer interrupt...
        MOV     W,RTCC-W
        BANK    sysREGS
        JNC     RTCISR          ;Yup, must be timer interrupt.
        MOV     RTCCQ,W         ;Nope, save current value minus 2 for later check.
;
        MODE    M_WKPND         ;Access port B pending registers... (M IS NOT RESTORED!!!)
        MOV     !RB,#%00000000

        ...

:CKRTC  MOV     W,#3            ;Will a timer rollover occur before the RETI?
        ADD     W,RTCC
        JC      :CKRTC          ;  Yes. Wait for it. (No carry when RTCC hits zero.)
        MOV     W,#2            ;Look at ISR entry value of RTCC.
        ADD     W,RTCCQ
        MOV     W,RTCC-W        ;Is the current value lower?
        JNC     RTCISR          ;  Yes: A rollover has occured.
        RETI                    ;  No: No rollover. Just get out.


RTCISR

        ...

:RTCEND MOV     W,#RTCON        ;Add constant to RTCC on way out for proper rate...
        RETIW

[/code]
This code, incidentally, used an RTCC prescalar rate of 1:4. Other prescale rates will entail different constants for detecting or anticipating an RTCC interrupt.

-Phil

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