Hi all,

If there is anyone here who knows VHDL well and is willing to answer a
few questions, please email me offlist (shb7 at cornell.edu).

Most importantly, I'm interested in race conditions and the effects of
routing delays on them and how to write VHDL to avoid them.

Thanks,

Sean
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist