> Software dude said.....the endurance of a flash is only related to
> the erase cycles, not the write cycles....ie....you get longer endurance
> if you only write thru a sector and then erase the entire sector..vs...
> erasing each location if you want/need to overwrite it.
>
> True or false?

For some reason I haven't received the original post, but if you're
quoting correctly, then it's true - he did say that ;-)

The topic has been covered here now and then, you should be able
to find previous discussions in the archives

Flash erase and write are inextricably linked. Take any PIC that
can write to its own Flash. For example, to change one Flash byte

- read the Flash block into RAM, modify the byte
- erase the Flash block
- write RAM back into the Flash


>From http://en.wikipedia.org/wiki/Flash_memory

Although technically a type of EEPROM, the term "EEPROM"
is generally used to refer specifically to non-flash EEPROM which
is erasable in small blocks, typically bytes
.....
One limitation of flash memory is that although it can be read or
programmed a byte or a word at a time in a random access
fashion, it must be erased a "block" at a time. This generally sets
all bits in the block to 1. Starting with a freshly erased block, any
location within that block can be programmed. However, once
a bit has been set to 0, only by erasing the entire block can it be
changed back to 1. In other words, flash memory (specifically
NOR flash) offers random-access read and programming
operations, but cannot offer arbitrary random-access rewrite or
erase operations

>From Microchip AN537 -

http://ww1.microchip.com/downloads/en/AppNotes/00537.pdf

Figure 1 illustrates a CMOS floating gate EEPROM cell, including
voltage conditions for READ, ERASE, and WRITE operations. To
erase or write, the row select transistor must have the relatively high
potential of 20V. This voltage is internally generated on chip by a
charge pump, with the only external voltage required being VDD.

The only difference between an ERASE and a WRITE is the direction
of the applied field potential relative to the polysilicon floating gate.

When 20V is applied to the polysilicon memory cell gate and 0V is
applied to the bit line drain (column), electrons tunnel from the
substrate through the 90-angstrom Tunnel Dielectric (TD) oxide to
the polysilicon floating gate until the polysilicon floating gate is
saturated with charge. The cell is now at an ERASE state of "1"

When 0V is applied to the polysilicon memory cell gate and 20V is
applied to the bit line drain (column), electrons tunnel from the
polysilicon floating gate through the TD oxide to the substrate. The
cell then is at a WRITE state of "0". This sequence of the transfer
of charge onto the floating gate (ERASE) and the electrical removal
of that charge from the floating gate (WRITE) is one ERASE/ WRITE
cycle, or "E/W cycle."

The field (applied voltage to an oxide thickness) across the tunneling
path created by the 20V potential is extremely high in order to
transfer the electrons. Over the cell's "application time," as measured
by E/W cycles, the EEPROM cell begins to wear out due to the field
stress.

The EEPROM cell wears out as the number of cycles increase
resulting in the voltage margin between the ERASE and WRITE
states decreasing until finally there is not enough margin for the
EEPROM sense amp to detect a difference in the two states during
a READ. Failure is defined as when the sense amp can no longer
reliably differentiate logic state changes


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