I'm also just getting started with fpgas. The company here is using
Altera, so that's what I'm now using. I looked at both vhdl and verilog
and am finding verilog much easier to use. A consultant showed me a pretty
easy way to write verilog code. It works for my hardware oriented mind.
You set up a bunch of registers (or flip flops) like this:

  // Define Registers
  reg [7:0] TxDataD;
  reg [7:0] TxDataQ;		// Data we latched from the processor and are
sending to fpga
  reg FpgaClockD;
  reg FpgaClockQ;			// This will toggle to clock data into external fpgas
  reg [2:0] ClocksPerByteD;
  reg [2:0] ClocksPerByteQ;	// how many clocks per byte. Do 1 for normal,
4 for compressed/encrypted
  reg [2:0] ClockCounterD;
  reg [2:0] ClockCounterQ;	// count down counter that counts clocks
  reg [1:0] StateD;
  reg [1:0] StateQ;			// state counter


For each, a D and Q is defined (like a D flip flop).

Then, reset and clock are dealt with. Reset clears everything. Clock
transfers D to Q on everything.

 // Handle reset and clock
  always @(posedge clk or negedge resetn) begin
    if(~resetn) begin		// we got a negative edge on resetn, so reset
everything
      TxDataQ=8'b00000000;	// outputs in some defined state
      FpgaClockQ=1'b0;		// set clock low
      ClocksPerByteQ=3'b001;// default to one clock per byte
      $display("Resetting %d", ClocksPerByteQ);
      ClockCounterQ=3'b001;	// assume we are going to send one clock
      StateQ=2'b00;			// nothing to send yet.
    end else begin			// not in reset, we must be on posedge clk, so
transfer all Ds to Q.
      TxDataQ=TxDataD;
      FpgaClockQ=FpgaClockD;
      ClocksPerByteQ=ClocksPerByteD;
      ClockCounterQ=ClockCounterD;
      StateQ=StateD;
    end						// end else
  end						// end always


Then the combinational logic defines the D inputs.

 // Combinatorial logic. Drive register D inputs
  always @(*) begin
    TxDataD=TxDataQ;			// Default action - loop q back to d to hold values
unless changed below
    FpgaClockD=FpgaClockQ;
    ClocksPerByteD=ClocksPerByteQ;
    ClockCounterD=ClockCounterQ;
    StateD=StateQ;
    case(StateQ)				// state machine
      2'b00: begin				// waiting for csn and wrn strobe
           if(~CSn) begin
             if(~wrn) begin
               if(RegSel) begin
                 ClocksPerByteD=DataIn[2:0];	// regsel=1, capture
ClocksPerByte
                 StateD=2'b11;				// go wait for write to go false
               end else begin
                 TxDataD=DataIn;			// RegSel low, capture data
                 ClockCounterD=ClocksPerByteQ; // Init the clock counter
                 StateD=2'b01;		// on to next state and go on to next state
               end
             end					// end if(~wrn)
           end						// end if(~csn)
         end						// end case 0
      2'b01: begin
           FpgaClockD=1'b1;			// drive clock high
           StateD=2'b10;			// on to next state
           ClockCounterD=ClockCounterQ-3'b001; // count down the clocks as
we send them
         end
      2'b10: begin

<snip/>

So, I've had a lot more luck with verilog instead of vhdl. Just the way my
brain works, or not.

For hardware, I'm using the Altera CycloneII FPGA Starter Board which has
a lot of I/O I'm not using, but also has some headers with I/O I can drive
my devices with.

So far, so good!

Harold




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