On 10/8/07, Jinx <joecolquitt@clear.net.nz> wrote:
> Can anyone suggest why this table write is successful in MPLAB
> but not in the real chip ?
>
> I have several Flash read/write routines for the 18F4550, and I
> can't see any address restrictions in the data sheet


The datasheet says the following.

The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the Row Erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write 32 bytes into the holding registers with
auto-increment.
7. Set the EECON1 register for the write operation:
=95 set EEPGD bit to point to program memory;
=95 clear the CFGS bit to access program memory;
=95 set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 through 14 once more to write
64 bytes.
15. Verify the memory (table read).
This procedure will require about 8 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.

It seems to me that you do not following all the steps,
specifically step 6.

Xiaofan

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