On Mon, 10 Sep 2007, Morgan Olsson wrote:

> After submitting a support ticket and poning we finally got an answer that explains problems:
>
> "
> Under certain conditions, the use of dual priority interrupts
> may cause a program instruction to be skipped entirely.
> This has only been observed when both of the following apply:
>
> * Both high and low interrupts are enabled, and
>
> * A high priority asynchronous interrupt occurs in the
>   following cycle after any low priority interrupts.
>
> The event causes the stack to get pushed twice,
> and will eventually result in an overflow.
>   "

That's a very old errata going back to the first generation of 18F
parts (circa 2002).  I'd be surprised if it were present in recent
silicon.

If you were getting hit by this errata, you'd know it, because you'd
have a hardware stack overflow, which causes a reset by default.

--
John W. Temples, III
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