Hi Luis, On 30/08/2007, Luis Moreira wrote: > I am looking to run a CPLD at 200 MHz and I am finding it difficult to > generate the CLK signal. I though about using a CLK multiplier, but I > would like to have a low pin count one, like a 8 pin device SMD if > possible. Doesn't the CPLD have an internal PLL? Regards, Peter -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist