In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Jared.Woolston wrote:

Yea for keeping them neatly synchronized I was thinking of using a TTL oscillator to drive a sufficiently speedy transistor or a logic level MOSFET and just let that drive the SX chips. 100 SX chips....theres a small chunk of change. I had planned on having an extremely large bank of EEPROM.  All being I2C and for a conservative estimate lets say each set of 8 EEPROM chips -most of the ones ive seen only support 3 bit addresses but my viewing is highly limited and very selective - has its own dedicated I2C bus. Removing the 2 lines its going to take for the data logging SX to get the data in the first place, I figure I can get roughly 17 banks of 8 EEPROM chips for a total of 136. As you said, there are paging time issues to deal with as well. Perhaps I will add a RAM bank as well, however, the data logging I am thinking of is less of second for second and more of for storing data of settings and calculated adaptations, all of which can then be read back into the system when appropriate. Also, it doesnt simply write data each time it recieves it, there is a small amount of processing which occurs, taking input from other SX chips to determine the 'weight' of the data and if it merits logging. Even more specifically, the 1MBps is exclusively for inter-SX communication, unless I happen to find an EEPROM which supports it.....really its intended solely to take load off of the other chips in the system (by reducing the time they spend communicating between each other and the data logging system.)

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