Walter Banks wrote:
> As soon as we start computing fractions of an instruction it
> opens the question of  should we be taking advantage of the
> instruction transfer edges to reduce jitter.

I'm not sure what you mean by instruction transfer edges, but any one
section of code can of course only take a integer number of instruction
cycles.  The user may need to be a little clever to eliminate long term
error, but this can still be done with abutting sections of specified
execution time.

In my case I wanted a average of 4.2 cycles per code section.  The low level
assembler macro just guaranteed some number of instruction cycles since a
label, assuming one address meant one instruction cycle, which was true in
my case.  Higher level assembly time logic in the top level source code did
the figuring of how many instruction cycles to specify for each bit.  This
same higher level logic could be applied on top of a HLL facility that
provided fixed timing for a block.

But again, do you really want to do this?


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