>> - Use complementary PWM on the two pins and low pass filter (or use
>> PWM so high that the result is inaudible).

> Switching a PWM for an inaudible signals equal creating EMI and
> noise
> on the board for nothing while some power is used for this.

Why do you say that? Using rail to rail PWM with multiple transitions
per output cycle to synthesise desired waveforms is the overwhelmingly
common method of providing eg AC motor control, and in many many other
systems that require analog output signals from a digital system.

EMI is a matter of design every time you toggle a port pin and could
be minimal in this case if reasonably implemented. While power
consumption does increase with switching rate this is highly likely to
be miniscule and irrelevant in this application.

Rather than being "for nothing" what it achieves is a potentially
hardware less solution to his requirement. This may be a very great
something depending on his exact requirement. eg if the products are
5000 km away and can be software upgraded easily or even perhaps
remotely and the customer just 'wants the buzzer quieter" then this
may be an extremely valuable solution.

I'd rate processing overhead as the biggest potential cost, and as he
says he has two complementary timer outputs available on the piuns
he's using, this is liable to not be much of an issue either.

This is an entirely standard and realistic solution.
It has the advantage of having either a zero or low parts count.


>> 2.    Another method will less processor load is to use one pin to
>> produce tone out and PWM modulate the other at a somewhat higher
>> frequency to chop the tone. Filtering needed to deal with nasty
>> intermod sounds. Single pin output halves transducer drive voltage
>> over toggled pair system and may reduce max sound level to 1/4
>> depending on transducer.

> This methode is often named one pin for frequency, one pin for
> amplitude
> and works on both situation when the piezo has or not a transformer.
> Is the best way to do it.

It is *a* way - which is why I suggested it :-).

Compared with my 1st suggestion it requires more (some) hardware and
probably less software and almost certainly less processing overhead.
The 2nd suggestion also reduces the output voltage from 2 x Vdd to Vdd
(2 pin complementary drive versus 1 pin drive) which reduces the power
into a given resistive load by a factor of 4. Whether this makes it
"best" depends on which constraints he values most. As he explicitly
asked for a zero hardware solution my first suggestion seems superior,
in the absence of extra information.

My method 3 is of similar nature and pros and cons compared to method
1 and has the advantage of no intermodulation problems.

>> 3.    A diode gate driven from a DC signal derived from control PWM
>> would lessen the PWM load and remove intermodulation problems.



        Russell


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