Jinx wrote:
> I think my findings show that 3.2768 is an entirely
> inappropriate crystal for OSC1/OSC2 and results in
> incorrect operation of the hardware (note how that
> previously ANY value written to TMR0 is ignored).
> Now that a crystal is there that, I'm surmising, the PLL
> can lock onto, the hardware is operating as it should

Well, 3.2768 is probably an entirely inappropriate frequency for the PLL 
input. I'm pretty sure the PIC doesn't care what frequency you plug it 
into without using the PLL, as long as it's within core spec.

Very nice information to know though. I didn't expect the 4550 PLL to be 
so picky. It's still strange though - why would TMR0 act weird, while 
instructions work normally? As you've mentioned, there's probably a 
logical explanation for all this in the silicon. We'll probably never 
find out though.

Mental note: 4Mhz ONLY really means 4Mhz ONLY.

-- 
Hector Martin (hector@marcansoft.com)
Public Key: http://www.marcansoft.com/marcan.asc

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