> If you look at the DataSheet carefully (Section 2.2.1 in the Figure
> 2.1), there is only one place where they mention that "4 MHz input
> only"

I'm still working that block out but it looks like you get 96MHz
only with a 4MHz input (ie output of the pre-scaler and MUX ?)

"The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input"

Parameter F13 might be the PLL lock range

F13 ?CLK CLKO Stability (Jitter) -0.25 - +0.25 %

If so then the frequency produced by 3.2768 is well out of spec

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