> Are you sure is not a problem of PLL lock ?

That's likely to be the cause, but when I thought of that earlier
I couldn't understand why general instructions execute at the
correct speed, for example the 1ms delay is good, but TMR0
doesn't increment correctly. And always a 757us rollover too.

I daresay there's a silicon component to all this, not simply
the clock. Anyway, hopefully I have found the problem and
can move on (it's been a very long two days)

On the plus side, I know more about the 4550 than I did
yesterday

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist