On 6/24/07, Jens M. Guessregen / Mailinglists
<jmg_mailinglists@mcm-it.de> wrote:
> > Well, your advices where stright forward.
> > The FPGA is 1 mm pitch with square distribution, I've guess
> > will be more than 200 routes. I've already done such designs
> > on 12 layers (0.5 and 0.4 mm pitch) but the price for PCB
> > manufacturing was huge so my intention is to avoid blind
> > microvia and if possible buried too... I'm wondering how can be done.
>
> Well, you are talking about 200 lines connected to the FPGA. How many of
> them are high speed, differental and impendance controlled?

I don't have yet the full picture, still working on it,  however will
be all the 3Gbps differential transcievers connected, some DDRAM2,
four gigabit ethernet ports,
some fast 32 bit bus, etc.


> What about the rest of pins? How many power,GND and sttic pullup/down's?

I'll know at the end of design. Design is mine too...
>
> I have seen designes with full connected 1000+ Xilinx FPGA's here on 12
> and 16 layers without blind and buried via's, but this depends realy on
> a lot of issues.

Yes, I've download and analised deeply some reference designs with
1100+ balls on 12 layers.

>
> By the way, high speed differental and impendance controlled busses on
> the outer layers is a bad idea, just making the layer stack very
> inflexible and expensive.

Doing it on the inner layer as stripline instead of microstrip on the
outer layers will be the same as long will be used only through holes
vias and back drilling is a complicated issue. A through vias on a
3Gbps line means an unwanted  stub between the used line and the
bottom layer.


>
> You should start with a clear stack setup for your impendance, then
> fanout all power and GND and then routing only the impendance controlled
> lines. After that, you can see, if you need additional layers for the
> rest or not.

Yes, but that starategy implies a very difficult stack-up
modification. I don't know what cad is your favourite, mine's is the
one company bought.

>
> If it is a XILINX, ask XILINX for their local layout reference partner.
> They have some partners, who are doing reference layouts on
> high-pin-count devices for XILINX. I know one of their partners (here at
> Germany) very well ;-)

okidoki, thx
>
> Best Jens
>
>
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