I would consider a design something like the following:

Master unit:

Output is driven to either V+ or left floating.
The output line is divided into 'bit times'.

Each bit time is used for one of four purposes:

a) Output a zero: 95% on, 5% off
b) Output a 1: 90% on, 10%off
c) Output a 'frame sync pulse': 85% on, 15%off
d) Accept an input bit: 80% on, 5% off, 10% driven by remote device, 5% off.


Slave unit:

Diode/capacitor used to keep V+ up internally.
To send an output bit the power/data line is driven, at the appropriate 
moment duing the bit time, to a voltage *less than* the V+ provided by the 
master. This voltage should be more than one diode drop less than the master 
output voltage so that it does not attempt to charge the capacitors in the 
other units.

The master can detect this 'less than V+' voltage at the appropriate moments 
to receive the bits from the slave units.

Bob Ammerman
RAm Systems


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