Mircea, I like this solution. Just curious, what Baud rate are you
using? The resistors won't pull the line to the '1' state as quickly
as the driver would.

BTW, I already have the resistors at each end of the bus, so I
wouldn't have to add them. Just need an inverter (i.e. your Q1) to
drive the enable from the TX data.

Neil

>
> When idle, the usart TX line is 5V, so Q1 is in conduction and the
> transceiver is in receive state. So you listen to the comms on the
> bus. When you send a byte on the usart at each 0V on TX line the
> transceiver goes in transmit state, it's data input is tied to ground
> and puts a 0 logic on the bus line. As soon as the bit ends it
> releases the line and goes in receive state.
> The bus has to be held in 1 logic by adding 2 more resistors at
> master's end (or you can distribute this resistors all over the
> network) from 485A line to +5V and from 485B line to GND.
>
> Hope it helps,
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