Neil I've also seen a hardware solution where the TX line from the processor is used to trigger a fast-attack switch to turn the TX on when it detects the start bit. It includes slow decay that delays the TX disable for about one byte length. The top speed is limited by the attack time but it was working fine at 38400b/s although the start bit gets truncated by a uS or so. RP On 15/06/07, Neil Baylis wrote: > Oh yes, I see now. Unfortunately, it doesn't generate an interrupt. > It's going to set about 100 usec after the last interrupt. (I'm doing > 115200 Baud). That's too long to just spin and wait. (My nodes are > pretty busy). > > But the receiver (who's going to send the next message) does get an > interrupt, and will be putting something on the wire very quickly, > within a few microseconds. > > It's looking like a timer of about 100 usec is the best option. I > would start the timer when I get the interrupt for the last > transmitted byte, and disable the transmitter when the timer expires. > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist