I had considered this flaw in the schematic as well.

My assumption is that there was an internal pull-up on A1. The only 
thing that could make sense.

Rolf


Russell McMahon wrote:
> I'll copy this from below as its crucial
>
> *** The turnoff of A0 must wait until after the button is released *** 
> or the still-pressed button will retrigger the circuit.
>
> _______________________
>
> There's a fundamental problem with the circuit diagram AND there's 
> almost certainly a problem with your circuit implementation.
> Adding a pullup on A1 makes the circuit operation defined and this may 
> have been specified elsewhere.
>
> All Off
>
> PNP = Q1
> NPN = Q2
> Upper diode = D1
> Lower diode = D2
>
> Button = ground diode junction on so PNP on so power on.
> PIC pits A0 high so NPN on so PNP held on and all is well.
>
> Now, A1 cannot either affect or see anything useful.
> It is behind two opposed diodes so it cannot drive Q2_c hi or low
>
> If A1 is input and Q2 is off then Q2_c is high but D2 blocks the Q2_C 
> high so A1 see's a floating switch.
> Pressing button changes A1 from float in to gnd in but this is not 
> overly useful at this stage.
>
> With Q2 on = power on then Q2C ~~= 0 volt so D1 cathode and D2 cathode 
> are at float.
> Again, closing button takes A1 from float to ground.
> A pullup on A1 allows the button press to be seen and then the 
> processor can turn power off using A0.
> *** The turnoff of A0 must wait until after the button is released *** 
> or the still-pressed button will retrigger the circuit.
>
> _____________
>
> With button open and no PIC then A1 *MUST* float. If it has a 10k 
> pullup it must pullup. If it doesn't the cct is not as shown.
>
> A P channel FET will work well as long as gate drive voltage is not 
> too high or too low.
>
>
>         Russell
>
>
>   

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