>I've guess there are people here which already did it.
>The question is which is the minimum number of layers
>for routing an 1738 balls FPGA witha couple of 3.1Gbps
>transcievers inside ?

I think you will find the answer is "lots" - and that will include using 
blind vias. I am thinking you are going to be into 20+ layers by the time 
you have enough ground plane layers for those high speed impedance matched 
signal lines. 

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