Well, if you only have to route 200 wires away from the chip, and the rest go to power, ground, or caps on the opposite side of the PCB, then you can do it with very few layers. Alternately, I've seen 26 layer boards that hold dozens of huge interconnected FPGAs. It also depends on the distribution of the balls, where the wires are going, how more board space is immediately outside the chip, and other circuit constraints (ie, you may need to keep all the lines in a given data bus to the same length). Lastly, there's a tradeoff between the cost of extra layers and blind and buried vias. Chances are you cannot complete the routing of such a huge chip without blind vias, and perhaps not without buried vias. If you go very small in drill size and trace/space, you may be able to eliminate a layer or two that you might otherwise have to add. So, in short, there's no rule of thumb I'm aware of that'll go from number of balls to layers of board. But if you decide to dead bug mount it for prototyping, be sure to send pictures to the list! :-P -Adam On 6/11/07, Vasile Surducan wrote: > I've guess there are people here which already did it. > The question is which is the minimum number of layers for routing an > 1738 balls FPGA witha couple of 3.1Gbps transcievers inside ? > > thx, > Vasile > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Moving in southeast Michigan? Buy my house: http://ubasics.com/house/ Interested in electronics? Check out the projects at http://ubasics.com Building your own house? Check out http://ubasics.com/home/ -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist