Jinx wrote:
> For this particular application I won't be using USB. It seems to
> me that the Fosc bits in CONFIG1H should enable HSPLL to
> provide a 32MHz primary clock or, as I originally intended, a
> 39.3216MHz primary, for the core. That said, what effect, if
> any, does CPUDIV have, being an output of the crystal's path
> through the USB clock section ?

CPUDIV always drives the CPU clock, both in PLL and nonPLL mode (with
different divider values). Maybe you're confusing the low-power T1OSC as
the main clock?

Also, the datasheet states that the PLL input should be 4Mhz exactly.
While it will probably work with slightly off values, it probably won't
with a lot more or a lot less. Seeing how you're using 8Mhz-ish clocks,
you'll want to set PLLDIV=2 to feed half of it to the PLL. The PLL will
multiply this *24, which gives you around 96Mhz. CPUDIV then scales this
down 2,3,4, or 6 times. PLLDIV=2, CPUDIV=OSC1_PLL2 will give you a 48Mhz
clock with an 8Mhz input. Use CPUDIV=OSC2_PLL3 if you want a slower
clock - combined with PLLDIV=2, this will get you a standard *4 overall
multiplier, which is probably what you wanted (and probably should work
with your original xtal).

I think your main problem is driving the PLL at 8Mhz, when it expects
4Mhz. Remember, this is not the usual *4 PLL that other PICs use - this
one does *24 (or *12, effectively, for the CPU, since you're always
forced to divide by two at least). If the core is then run at /2, and
assuming the PLL copes (192Mhz!), you get the core running at 96Mhz. I'm
surprised it even did anything resembling proper operation at that speed ;)


-- 
Hector Martin (hector@marcansoft.com)
Public Key: http://www.marcansoft.com/marcan.asc

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