Jinx wrote:

> It seems to
> me that the Fosc bits in CONFIG1H should enable HSPLL to
> provide a 32MHz primary clock or, as I originally intended, a
> 39.3216MHz primary, for the core.

Note that the PLL in these parts are a fixed 4 MHz -> 96 MHz
PLL. Other (non-USB PIC18) parts can use different input
frequencies to it's PLL circuit.

So 8 MHz xtal and 2/ PLL-prescaler is fine, but probebly not
a 9.8 MHz xtal, sice it can't be divided down to 4.0 MHz.


> That said, what effect, if
> any, does CPUDIV have, being an output of the crystal's path
> through the USB clock section ?

The output from the PLL-postscaler (which CPUDIV controles)
goes to the CPU clock section, not to the USB clock section.
(It can be routed back to the USB clock section by FSEN, but
that is later in the clock-chain.)

So CPUDIV controles primarily the speed of the CPU as a
devided down frequency from the USB-clock.

Or did I missunderstod the question ?

Jan-Erik.

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