> Hi Jinx, its ocillator is very different from 452... and 4520 too, due 
> to the USB thing

> Apart from that, yes, it should work similarly.

OK, here's where we're up to. Think I need some pointers. I've
read the d/s oscillator section again. Without a couple of clues
though I don't know what I can disregard

As I said, I dropped to 8MHz on OSC1,2 and there is now some
activity on the LCD lines, but it isn't what I expected and it isn't
consistent either. The 100ms delay I call between operations varies
between just a few ms and 45ms after a reset (which triggers the
analyser), so something's not stable

I'm trying to work my way through Figure 2.1 of DS39632B

For this particular application I won't be using USB. It seems to
me that the Fosc bits in CONFIG1H should enable HSPLL to
provide a 32MHz primary clock or, as I originally intended, a
39.3216MHz primary, for the core. That said, what effect, if
any, does CPUDIV have, being an output of the crystal's path
through the USB clock section ?

TIA

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