On 6/8/07, Herbert Graf <mailinglist3@farcite.net> wrote:
> On Fri, 2007-06-08 at 15:01 -0700, Harold Hallikainen wrote:
> > I'm working on my first project with JTAG. I managed to use onTap to find
> > some problems between a PowerPC and flash memory today. That was great!
> > Anyway, there is concern that if we make one big JTAG loop, it will not
> > work if there is anything wrong anywhere on the loop. I'm thinking we
> > could stick resistors between the serial data out of one chip and the
> > serial data in of the next, then put a single JTAG header for the whole
> > board and also headers for each chip. When driving an individual chip, the
> > serial data out of the previous chip would be "overpowered" by the JTAG
> > "probe" serial data out.
> >
> > Is this workable? Is anyone doing anything like this? What value resistor?
>
> I don't like it, there are too many areas to "go wrong" IMHO (i.e.
> what's the output impedance of the chip, what's the output impedance of
> your JTAG cable, what about a different JTAG cable?).
>
> I've worked with boards where 0ohm resistor were used to "configure" the
> board with regards to the "shape" of the loop. Jumpers can also be used.
>
> Personally I don't see the point. I've never seen a problem with a JTAG
> loop, and this is on board with 6 seperate JTAG devices on it, in one
> big loop.

There is one big question: are those 6 jtags identical, used for the
same type of
FPGAs ? My problem is that some devices (like DSPs) are not using a
standard JTAG configuration, so common use of chained jtag loops could
bring a lot of problems.
However it's about FPGA, because that word wasn't mention in your posts ?
Harold solution is a common one, reconfigure everything with 0 ohm
bridges and a chance to work from the first PCB iteration.

Vasile
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