Sure,

Last 3 weeks I was working with SPI interface to communicate with 
external ADC and co processor. What I noticed that each device has
it's own requirement. Some of them speed doesn't matter and some will
give you a limit so to answer to your question depending on what chip
are you going to talk to may require different setup like clock out @
falling edge and data in on rising edge etc. 

Andre 



-----Original Message-----
From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu]On Behalf
Of Ira Burton
Sent: Saturday, May 26, 2007 8:30 PM
To: piclist@mit.edu
Subject: [PIC] SPI Clock


I asked this question once before in a slightly modified manner and never
received a response so I thought I would try again.

I have two PIC processors running at different speeds.  One is running at
8MHz using the internal clock and another is running at 40MHz (via PLL).  My
question is if I use the faster PIC as the master can I reliably send data
to the slower as long as I don't exceed the slower processors processing
capability.

I have built a simple test circuit that appears to work, but I want to make
sure that it is "within spec."  I cannot find reference to this in any data
sheet or other document.  I need to make sure this would be reliable in the
real world.

Any thoughts?
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