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> You cannot simply create a voltage which is 12V above your supply rail
> and feed that to your high-side fet gates (at least not without a
> zener clamp on each one). This is because initially, when the source
> of the high side fet is at 0V, applying Vsupply+12 to the gate would
> cause Vsupply+12 of gate-source voltage on the high-side fets. This
> would only be for perhaps 100 nanoseconds or so, but could be enough
> to punch through the ultra-thin gate oxide layer (due to violation of
> Vgs_max spec).
can't you just select fets that are suitable for a gate source voltage of vsupply+12
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