Yeah, I thought there would have been more comments about this. This issue has been simmering for ever. But things have got worse not better. Microchips message "don't use" the ESD diodes message is more than a little dissapointing. As discussed already, it is near impossible to design simple cost/space effective input/output clamping circuits to achieve the absolute maximum specs of Vss-0.3 to Vdd + 0.3v. That takes away the attractiveness of the PIC in small, single chip, real world interface designs, for which they are supposed to be ideal. What we assumed to be rugged, reliable I/O hardware should now be re-categorised as fragile and flaky. Brent. On 13 Apr 2007 at 9:43, Vasile Surducan wrote: > So finally it's light... > :) > > On 4/13/07, Brent Brown wrote: > > Microchip says... > > > > "The current datasheets specify Vss-0.3 to Vdd + 0.3v" > > > > "If you start curve tracing the devices you will find that the ESD > > protection diodes clamp at 0.6v. The 0.3v specification is intended > > to prevent the input protection diodes from conducting. We have > > learned that as more analog peripherals are placed on the device, > > including low power POR/BOR circuits, the currents created when the > > ESD diodes clamp can cause very bad behavior. In one example, the > > POR circuit asserted POR when the ESD diodes were conducted. We do > > not want the ESD diodes conducting so we have specified the voltage > > range more tightly." > > -- Brent Brown, Electronic Design Solutions 16 English Street, St Andrews, Hamilton 3200, New Zealand Ph: +64 7 849 0069 Fax: +64 7 849 0071 Cell: 027 433 4069 eMail: brent.brown@clear.net.nz -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist