In SX Microcontrollers, SX/B Compiler and SX-Key Tool, DragonSX wrote:

I have been looking for more information on the reset for the SX48BD.  After getting my hopes up a little when it talked about "For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT2:WDRT0 field to 100."  I noticed that this did not match the datasheet for the SX48BD.  My datasheet specifies an 2-bit DRT field.  Also, there seems to be differences in the minimum DRT time.  One datasheet floating around says 250uS and another says 60uS.  My experiments with the SX48BD seems to give me closer to 250uS. 

The doc dkemppai posted seems to have been dated year 2000.  Was there a change in design at sometime?  Is there anyway I can get the SX48BD to have zero startup delay?

-Matt

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