Wouter van Ooijen wrote:
>> (See, I predicted you'd say "Yuck"!)
> 
> both clever and yuck (I like clever!)

I'm glad to get at least some clever with the yuck!

> A problem: when the receiver reads the bit value it waits for the A/D to
> raise over 59, then reads either 59..77, or 50%. But when you read
> 59..77, how do you know that the voltage is not 'on its way' to 50%?
> What might help is first wait until it is within 59..77, and then wait
> at least a certain amountr f time, and then measure again. I don't like
> this, it re-introduces time...

Good point.  You could specify two consecutive reads that are "close," 
figuring that rise time to 50% will be generally be far shorter than one 
A/D cycle time (again, dependent on short transmission lines and low 
capacitance).

> Note that the above is a general problem when a state change passes
> through intermediate states.

Right.  One good reason why trinary never caught on.

> Logically it is not that different from the 2 OC lines, so I think it
> probably has the same problem: how to arbitrate the half-duplex flow?

Yes.  Again, I think the trade-off is to require something in the higher 
level protocol - a token kind of thing.  It seems acceptable to me.

The original motivation was that I had two old boards that, together, 
could solve a new problem - but I only had access to a couple of pins on 
each board's PIC.  In this case, it's OK to have the master update the 
slave's status, then every now and then say, "By the way, has anything 
changed on your end?", receive one status byte, and gain control back.
-- 
Timothy J. Weber
http://timothyweber.org
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