> (See, I predicted you'd say "Yuck"!)

both clever and yuck (I like clever!)

A problem: when the receiver reads the bit value it waits for the A/D to
raise over 59, then reads either 59..77, or 50%. But when you read
59..77, how do you know that the voltage is not 'on its way' to 50%?
What might help is first wait until it is within 59..77, and then wait
at least a certain amountr f time, and then measure again. I don't like
this, it re-introduces time...

Note that the above is a general problem when a state change passes
through intermediate states.

Logically it is not that different from the 2 OC lines, so I think it
probably has the same problem: how to arbitrate the half-duplex flow?

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: www.voti.nl/hvu
 

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist