> Did you ever run into this "bypass solution"?
>
> VCC------------------------------------------------------------------- 
> ---
>         Chip       Chip           Chip         Chip
> GND------------------------------------------------------------------- 
> ---
>         cap        cap             cap           cap
> VCC------------------------------------------------------------------- 
> ---
>         Chip       Chip            Chip        Chip
>

That was quite a standard way of doing things for TTL, and the habit has 
continued into the CMOS era, although it is quite possible to get away with 
about a 1/4 the number of caps for CMOS, as a rule of thumb.

For TTL the "generally accepted rule" was to have a 47nF to 100nF per chip, 
normally put at one end of the chip. Suitable caps also tended to have a 
0.3" lead spacing so they fitted the same grid as the chips. Remember that 
TTL has quite high switching current spikes.

Another trick used on large boards was additional power distribution strips 
consisting of two layers of metal separated by a thin insulation layer. 
These allowed a higher current carrying capacity than the PCB tracks, and 
had the added advantage of being a long distributed bypass capacitor. This 
was in addition to the capacitor per chip.

The other part of the "general rule" was to have large bulk capacitors, 
10-100uF at each corner of the PCB, and if the PCB was large enough to need 
stiffeners, then more bulk capacitors were fitted where the stiffener went 
across. These served to deal with "long term" current surges, especially on 
memory boards where there was a hefty current draw during the refresh cycle, 
where most refresh schemes did all chips simultaneously. 

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