On Mon, 2007-01-29 at 23:37 -0500, Paul Anderson wrote:
> Here's a pretty basic question for the list.  What is the difference
> between an FPGA and a CPLD?

The difference used to be very well defined, these days it's getting a
little fuzzy.

You can get some insight from the naming:
CPLD - Complex Programmable Logic Device
FPGA - Field Programmable Gate Array

>From the naming you can see that CPLDs tend to be a little more
"complex". The "blocks" (they have various names, macrocell is common)
generally have a relatively large amount of logic in them. This is both
good and bad. If your logic maps nicely into a macrocell you can pack a
surprising amount of logic in these parts. If your logic doesn't map
nicely you can easily run out of space.

CPLDs generally are smaller in "gate count" then FPGAs, have lower pin
counts, usually have a few hobbyist friendlyish packages (PLCC) and
often can't run as fast. That said, they are usually cheaper and easier
to use (they hold their configuration with power off, most FPGAs need
external PROMs to hold the configuration which is then bootstrapped on
powerup) and are less complicated in power requirements (usually single
rail if you select a device whose core voltage matches your IO voltage,
otherwise typically two rails).

FPGAs OTOH are more "simple" in nature. Their "blocks" (often called
slices) usually only have a LUT or two, a few flops and maybe some
inverters. That said they have alot of these slices, meaning they are
more general; more logic will have a chance of an efficient mapping then
on a CPLD. 

They are generally larger, both in gate count and physical size then
CPLDs. Packages generally range from hobbyist unfriendly (TQFP) to
nearly hobbyist impossible (BGA). Their configuration memory is usually
SRAM, meaning you need to load the config on every power cycle (either
through JTAG or through PROMs or other bootstrapping solutions). Larger
parts often need multiple PROMs, which can really start eating board
space. There are some FPGAs these days with FLASH for configuration
memory, but that's relatively rare, and never on the largest parts.
Power generally is at least two rails (typically one for the core, at
least one for IO, sometimes one for another internal rail). If you are
running multiple IO voltages you'll need a rail for each bank that runs
at the different voltage.

If you are new to programmable logic I recommend starting with CPLDs.
They are "big enough" for the typical beginner projects and are easier
to handle (compile times are in the seconds, pin counts are lower,
cheaper).

A simple example of "useful" code that easily fits in a small CPLD is in
my logan project:

http://repatch.dyndns.org:8383/pic_stuff/logan

This was a project I built a few years ago using a 16F877 for most of
the control, and a CPLD for address generation, strobe generation and
clock switching. The code for the CPLD can be found in the
logic_analyzer.v file.

Hope this helped. TTYL



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